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MOSAID TECHNOLOGIES INC. v. SAMSUNG ELECTRONICS CO.

April 1, 2005.

MOSAID TECHNOLOGIES INCORPORATED, Plaintiff,
v.
SAMSUNG ELECTRONICS CO., LTD., SAMSUNG ELECTRONICS AMERICA, INC., SAMSUNG SEMICONDUCTOR, INC., and SAMSUNG AUSTIN SEMICONDUCTOR, L.P., Defendants. INFINEON TECHNOLOGIES NORTH AMERICA CORP., Plaintiff, v. MOSAID TECHNOLOGIES INCORPORATED, Defendant. MOSAID TECHNOLOGIES INCORPORATED, Counterclaimant, v. INFINEON TECHNOLOGIES NORTH AMERICA CORP., INFINEON TECHNOLOGIES AG, INFINEON TECHNOLOGIES HOLDING NORTH AMERICA CORP., and INFINEON TECHNOLOGIES RICHMOND LLP, Counterdefendants.



The opinion of the court was delivered by: WILLIAM J. MARTINI, District Judge

OPINION

INTRODUCTION

  This matter comes before the Court on the parties' motions for summary judgment. MOSAID Technologies Inc. ("MOSAID") seeks summary judgment of infringement as to claim 15 of the Lines '643 patent and claim 1 of the Foss '654 patent, and on several of Infineon Technologies North America Corp. et al.'s ("Infineon's") invalidity and unenforceability defenses, including invalidity under §§ 102(b) and (g), prosecution laches, and inequitable conduct. Infineon seeks summary judgment of noninfringement as to all of the asserted Lines and Foss claims, and on its claim that MOSAID's potential damages are limited under the patent marking statute. Also before the Court is MOSAID's motion to strike the Rebuttal Expert Report of Joseph McAlexander Regarding Non-Infringement of MOSAID Patents or, in the alternative, for leave to supplement the expert report of David Taylor. For the following reasons, the parties' motions for summary judgment are GRANTED-IN-PART and DENIED-IN-PART, and MOSAID's motion to strike is DENIED in its entirety. BACKGROUND

  This is a patent infringement action. Currently, MOSAID asserts that Infineon infringes seven patents. Those patents can be broken down into two families named after the lead inventors: the Lines patent family and the Foss patent family. The asserted Lines patents are U.S. Patent Nos. 5,822,253 (the "'253 patent"), 5,751,643 (the "'643 patent"), 6,278,640 (the "'640 patent"), and 6,603,703 (the "'703 patent"). The asserted Foss patents are U.S. Patent Nos. 5,828,620 (the "'620 patent"), 6,055,201 (the "'201 patent"), and 6,580,654 (the "'654 patent"). Both families claim particular circuits found in a DRAM chip; the Lines patents claim a word line driver circuit and the Foss patents claim a voltage pump circuit.*fn1

  This litigation began when Infineon filed a declaratory judgment patent action against MOSAID in the U.S. District Court for the Northern District of California. Aware that MOSAID had already filed a patent infringement action against Samsung Electronics Co. et al. ("Samsung") in this district, Infineon sought to consolidate the two cases as a multidistrict litigation in the California court. The Judicial Panel on Multidistrict Litigation agreed that it should be consolidated, but found that the District of New Jersey was the more appropriate court to conduct all pretrial proceedings. Accordingly, the Infineon action was transferred to this Court where it was consolidated with the Samsung action.*fn2 The only pretrial proceeding that remains to be completed is resolution of the pending summary judgment motions and MOSAID's motion to strike. This Court has conducted Markman proceedings and issued a Markman Opinion. The parties have completed fact and expert discovery. Once these motions are resolved, it will then be appropriate for the Infineon action to be transferred back to the Northern District of California.

  SUMMARY JUDGMENT STANDARD

  Patent cases are amenable to summary judgment. Knoll Pharm. Co. v. Teva Pharm. USA, Inc., 367 F.3d 1381, 1384 (Fed. Cir. 2004). Summary judgment eliminates unfounded claims without resorting to a costly and lengthy trial. Celotex Corp. v. Catrett, 477 U.S. 317, 327 (1986). However, a court should grant summary judgment only "if the pleadings, depositions, answers to interrogatories, and admissions on file, together with the affidavits, if any, show that there is no genuine issue as to any material fact and that the moving party is entitled to judgment as a matter of law." Fed.R.Civ.P. 56(c). The burden of showing that no genuine issue of material fact exists rests initially on the moving party. Celotex, 477 U.S. at 323. A litigant may discharge this burden by exposing "the absence of evidence to support the nonmoving party's case." Id. at 325. In evaluating a summary judgment motion, a court must view all evidence in the light most favorable to the nonmoving party. Matsushita Elec. Indus. Co. v. Zenith Radio Corp., 475 U.S. 574, 587 (1986); Goodman v. Mead Johnson & Co., 534 F.2d 566, 573 (3d Cir. 1976).

  Once the moving party has made a properly supported motion for summary judgment, the burden shifts to the nonmoving party to "set forth specific facts showing that there is a genuine issue for trial." Fed.R.Civ.P. 56(e); Anderson v. Liberty Lobby, Inc., 477 U.S. 242, 247-48 (1986). The substantive law determines which facts are material. Anderson, 477 U.S. at 248. "Only disputes over facts that might affect the outcome of the suit under the governing law will properly preclude the entry of summary judgment." Id. No issue for trial exists unless the nonmoving party can demonstrate sufficient evidence favoring it such that a reasonable jury could return a verdict in that party's favor. Id. at 249; Knoll Pharm. Co., 367 F.3d at 1384.

  DISCUSSION

  I. INFRINGEMENT

  MOSAID seeks summary judgment that Infineon's 256 RLDRAM Blaze ("Blaze") products infringe claim 15 of the Lines '643 patent and that Infineon's 256M Hatteras ("Hatteras") products infringe claim 1 of the Foss '654 patent. Infineon seeks summary judgment that the accused products do not infringe any of the asserted Lines claims that contain a "latching" limitation, any of the asserted Foss patents because of the "clock source" disclaimer, or claims 1 and 10 of the Foss '201 patent because of the "switching means" limitation. Infineon also seeks summary judgment that MOSAID cannot demonstrate infringement under the doctrine of equivalents for any asserted claim of the patents in suit. Because of the substantial overlap among these arguments, the Court will address them together by issue.

  Infringement is a two-step process: the Court must construe the disputed terms contained in the asserted claims, and then compare the asserted claims as construed to the accused products or processes. NTP, Inc. v. Research in Motion, Ltd., 392 F.3d 1336, 1364 (Fed. Cir. 2004). Because the Court has already completed the first step by construing the disputed claim terms in its Markman Opinion and Order, the Court now turns to the second step.

  To prove infringement, the patentee must show that the accused products or processes contain each and every limitation of the asserted claims, either literally or under the doctrine of equivalents. Frank's Casing Crew & Rental Tools, Inc. v. Weatherfood Int'l, Inc., 389 F.3d 1370, 1378 (Fed. Cir. 2004). A product or process literally contains a limitation when it contains the limitation exactly. Litton Sys., Inc. v. Honeywell, Inc., 140 F.3d 1449, 1454 (Fed. Cir. 1998). If the limitation is not met exactly, it may still be infringed under the doctrine of equivalents. A product or process infringes a limitation under the doctrine of equivalents when some element of the product or process is not substantially different from the limitation (the "insubstantial differences" test),*fn3 or performs substantially the same function in substantially the same way to obtain substantially the same result as that limitation (the "function-way-result" test). Lear Siegler, Inc. v. Sealy Mattress Co. of Mich., Inc., 873 F.2d 1422, 1425 (Fed. Cir. 1989).

  A. Claim 15 of the Lines '643 Patent

  Claim 15 of the Lines '643 patent states:
A method of selecting a word line in a dynamic random access memory comprising:
decoding address signals to drive first and second level shifted control signals to logic levels including a voltage level greater than the voltage to be stored in a memory cell and latching the levelshifted control signals, each control signal in a respective latch state being pulled down to a low level through an N-channel transistor as the other control signal is latched high through a Pchannel pull-up transistor, the control signal being set and reset by pull-down transistors gated only by Vdd level signals; and
from one of the latched, level-shifted control signals applying a controlled high voltage greater than the stored voltage to a selected word line.
'643 patent, claim 15 (emphasis added). Infineon argues that the accused products do not infringe claim 15 because they do not meet the two italicized limitations. MOSAID disagrees, arguing that both limitations are satisfied by Infineon's accused products.

  1. Direct Versus Indirect Infringement

  As an initial matter, it is important to address Infineon's argument that MOSAID's motion for summary judgment of infringement should be denied because MOSAID has failed to proffer evidence that Infineon actually practices the method of claim 15. (Infineon's Mem. In Opp'n to MOSAID's Motions for Summ. J. Against Infineon ("Infineon's Opp'n Br.") at 2-3). MOSAID essentially admits as much, but responds by arguing that Infineon has induced others to infringe and has contributed to their infringement by selling in the United States DRAM products that perform the claimed method. See 35 U.S.C. §§ 271(b) (induced infringement) and (c) (contributory infringement). Since this lawsuit appears to be based on Infineon's sales of allegedly infringing DRAM chips in the United States, and MOSAID has not shown that Infineon practices the claimed method in the United States, the Court finds that Infineon does not directly infringe claim 15. Infineon, however, remains potentially liable for indirectly infringing claim 15. 2. The "Latching" Limitation

  The asserted claims of the Lines '253, '643 and '640 patents contain a "latching" limitation.*fn4 Claim 15 of the '643 patent is a representative claim. As set forth above, it requires that the level-shifted control signals be "latched." Infineon argues that none of the accused products "latch" the level-shifted control signals under the Court's construction of that term in the Markman Opinion and Order. MOSAID disagrees. MOSAID argues that Infineon misunderstands the construction of the "latching" limitation and that, if properly applied to the accused products, they infringe literally or under the doctrine of equivalents.

  In determining whether Infineon's accused products "latch" the control signals, the issue boils down to what it means to "latch" the control signals. Although the Court believes that this was clearly delineated in its Markman Opinion and Order, both parties argue that the Court's construction of "latch" supports their infringement argument.

  The Court defined "to . . . latch" as meaning "to indefinitely retain at least one data state with a feedback loop in the absence of any new control signal to change the state." (Markman Order at ¶ 22). MOSAID argues that this construction does not mean that the output state should be retained in the absence of inputs or "without input signals." Instead, it argues that the Court's construction "only requires maintaining at least one data state until a new signal changes the state." (MOSAID's Br. in Opp'n to Infineon's Motion for Summ. J. ("MOSAID's Opp'n Br.") at 8). As a result, it argues that cross-coupled PMOS transistors, such as p5 and p6 in Figure 1 of the '643 patent, are capable of "latching" control signals as defined by the Court. MOSAID's take on the Court's claim construction is incorrect. Essentially, MOSAID contorts the construction of "latching" in an attempt to reclaim a construction that was previously rejected by this Court. In doing so, it ignores the clear language of the Court's Markman Opinion, which contradicts MOSAID's current position.

  Previously, MOSAID contended that a "latching level shifter" holds the output signals while the input signals are present. (Markman Op. at 43-44). In an effort to persuade the Court that its proposed definition was correct, MOSAID argued that the dictionary definition of "latch," which referred to a symmetrical circuit, was inapplicable to this case because Figure 1 does not use a symmetrical latching level shifter; instead, it uses an asymmetrical latching level shifter. In other words, MOSAID acknowledged that Figure 1 was not capable of "two-way latching" under the ordinary meaning of the word "latch." MOSAID argued that Figure 1 shows an asymmetrical circuit capable of only "one-way latching" because it can only hold one output state in the absence of inputs. MOSAID contended that in order for Figure 1 to retain both output states, it would need another pull-down transistor, like transistor 12, whose gate is connected to node 8B.

  Indeed, MOSAID's own expert, Richard Greene, stated the following when explaining what a DRAM designer in 1990 would have understood the term "level shifter" to mean:

  Generally, a "latch" is understood to refer to a circuit that retains its output state in the absence of inputs. In contrast, the level shifter 6 shown in Figure 1 does not retain its output state in the absence of inputs. Rather, the level shifter 6 can not retain state because it only has one pull-down transistor 12 connected to the gate of one of the pull-up transistors 7B. In order to retain a logic zero, another pull-down transistor connected to the gate of transistor 7A would be required. (Expert Report of Richard Greene in Support of MOSAID's Claim Construction Br. ("Greene Markman Expert Report") at ¶ 18, emphasis added).

  In the Markman Opinion, the Court agreed with MOSAID's understanding of Figure 1. It determined that transistor 12 was an essential element needed to "latch" an output state and that the absence of a second pull-down transistor prevented Figure 1 from performing "two-way latching." The Court found that the latching level shifter of Figure 1 of the Lines patents can only retain one output state in the absence of input signals. (Markman Op. at 44). Relying in part on MOSAID's own expert's definition of "latch," the Court concluded that "latching" means "retaining an output state in the absence of inputs," i.e., retaining an output state without any input signals. (Markman Op. at 44 n. 20). This construction reflected the Court's view of how Figure 1 of the Lines patents works.

  In direct contrast to that construction, MOSAID's current infringement argument is predicated on the assertion that transistor 12 is not needed for latching. Indeed, MOSAID goes so far as to say that transistor 12 is "irrelevant" to latching,*fn5 and is but a "distraction, not a defense."*fn6 Instead, MOSAID argues that Infineon's Blaze "latches" the control signals by maintaining the inputs to the level shifter. (See, e.g., MOSAID's Br. Against Infineon at 8; Expert Report of David L. Taylor Regarding Infringement of the Accused Infineon Products ("Taylor Infr. Report") at ¶ 127). But that argument cannot be correct. If MOSAID's infringement argument was adopted, it would mean that Figure 1 performs "two-way latching" rather than only "one-way latching." In other words, MOSAID artfully twists the Court's claim construction until it achieves the same result it attempted to achieve under its proposed Markman construction.*fn7 Having rejected that proposition once, the Court readily and easily rejects the repackaged "latching" argument a second time. Consequently, because "latching" is not dependent on input signals being maintained, MOSAID's motion for summary judgment of infringement as to claim 15 of the '643 patent is denied.

  Given the correct construction of the relevant claim terms — that "latching" must be performed in the absence of input signals*fn8 — it is apparent that the only way to indefinitely retain a data state is to use a pull-down transistor such as transistor 12. To latch each control signal, the latching level shifter requires two pull-down transistors or other structure that performs that function. Here, there is no dispute that the level shifters in Infineon's accused products cannot indefinitely retain data states in the absence of inputs; they do not contain the requisite pull-down transistors. Thus, the accused products do not literally meet the "latching" limitation. Additionally, because MOSAID has failed to identify any other structure that can "latch" the control signals as defined by the Court, the accused products do not infringe the "latching" limitation under the doctrine of equivalents. Accordingly, the accused products do not infringe claims 31-34 of the '253 patent, claims 1-3, 8-13, 15-17, and 22-28 of the '643 patent, and claim 1 of the '640 patent, either literally or under the doctrine of equivalents.

  3. The "Control Signals Applying" Limitation

  MOSAID argues that Infineon's Blaze infringes the "control signals applying" limitation of claim 15 of the Lines '643 patent because Blaze's level shifter generates control signals that select a block of word lines, one of which is eventually selected by a primary and secondary decoder. Infineon argues that Blaze does not infringe this limitation because the signals identified by MOSAID are not control signals, i.e., they do not control the application of a voltage to a single word line or group of word lines.

  "Control signals" have been defined as meaning "signals used to control the application of a voltage to a single word line or a group of word lines." (Markman Order at ¶ 18). In the context of the claim language set forth above, the control signal applies Vpp to a selected word line. See '643 patent, claim 15. Here, MOSAID admits that Infineon's control signal only applies Vpp to a block of word lines, not a selected word line or even a group of word lines. (See MOSAID's Br. Against Infineon at 11-12). Once that block of word lines is selected, a primary and secondary decoder must then go on to select the appropriate word line or group of word lines. Since the signals identified by MOSAID do not apply Vpp to a selected word line, but are further upstream from the actual selection of the word line, those signals cannot be "control signals" as claimed by the patent. Therefore, Infineon's Blaze does not literally infringe the "control signals applying" limitation.

  B. Claim 1 of the Foss '654 patent

  Claim 1 of the Foss '654 patent states:
A dynamic random access memory (DRAM) boosted voltage word line supply comprising:
DC voltage supply;
a boosting capacitor having first and second terminals; and
a switching circuit including a first switch between the voltage supply and the first terminal of the boosting capacitor and a [1] second switch between the first terminal of the boosting capacitor and a capacitive load, the [2] first switch and the second switch being driven by clock signals, the [3] switching circuit alternately connecting the first terminal of the boosting capacitor to a first voltage level and to the capacitive load while alternating the level of voltage applied to the second terminal of the boosting capacitor to pump the voltage on the capacitive load to a boosted voltage level greater than and of the same polarity as the DC voltage supply, the second switch being enabled to substantially eliminate a threshold voltage reduction of boosted voltage; and
a word line decoder which selectively couples the boosted voltage level to a selected DRAM word line.
'654 patent, claim 1 (emphasis added).*fn9 MOSAID argues that Infineon's Hatteras infringes this claim. Infineon disagrees. Infineon argues that the accused products, including Hatteras, do not infringe any of the Foss patents because they fall within the clock sources disclaimer and therefore cannot meet limitation [3] designated above. Further, Infineon argues that Hatteras does not meet limitations [1] and [2] listed above.

  1. The "Switching Circuit . . . Alternating the Level" Limitation and the Clock Sources Disclaimer

  Infineon moves for summary judgment that its accused products do not infringe any of the asserted claims of the Foss '620, '201 and '654 patents. Each of these claims contains a "switching circuit . . . alternating the level of voltage applied to the second terminal of the boosting capacitor" limitation.*fn10 Infineon argues that its accused products do not infringe that limitation because they use a "clock source" to charge the second terminal of the boosting capacitor, and thus falls within the clock sources disclaimer. MOSAID responds by arguing that the accused products use a local "clock signal," not a "clock source," to charge the second terminal, which is fundamentally different and meets this limitation. In order to resolve this dispute, it is necessary for the Court to explicate what it means to use a "clock source" to charge a boosting capacitor.

  The Court construed "switching circuit . . . alternating the level" to mean "alternately connecting the second terminal of the boosting capacitor . . . without the use of clock sources to charge the boosting capacitor." (Markman Order at ¶ 26, emphasis added). This clock sources disclaimer applies to all of the Foss patents. (Markman Op. at 52-55). Figure 1 of the Foss patents is a drawing of a prior art circuit that used clock sources to charge the boosting capacitor. (See, e.g., Foss 30(b)(6) Dep. at 121:21-122:6).

  Infineon argues that the accused products work the same way as the prior art depicted in Figure 1. Although Infineon's products use intervening circuitry, including multiple inverters, charged by a "clock source" to supply the charge to the second terminal of the boosting capacitor, Infineon asserts that its products are no different than the prior art. According to Infineon, the inclusion of additional intervening circuitry does not alter the "clock source" in a meaningful way — the charge applied to the second terminal of the boosting capacitor remains a "clock source." Since the Foss patents disclaimed the use of a "clock source" to charge the boosting capacitor, Infineon argues that Hatteras and the other accused products do not infringe the asserted Foss claims.

  MOSAID responds by arguing that the accused products charge the boosting capacitor from local "clock signals," not "clock sources." MOSAID argues that Infineon misinterprets the phrase "clock sources" to include "clock signals." According to MOSAID, these are two different and distinct concepts. MOSAID argues that a "clock signal" is a voltage, whereas a "clock source" is structure, i.e., a circuit, which in the Foss patents refers only to the "master clock source," a circuit responsible for establishing the overall timing of all local "clock signals."

  One problem with MOSAID's argument is that the Foss patents' specifications use the terms "clock sources" and "clock signals" interchangeably.*fn11 See, e.g., '654 patent at 1:40-42; 1:51-58; 4:28-41; 5:24-30; 6:30-32. One conspicuous example of how the terms are used interchangeably to refer to a voltage is:
Clock sources are applied to the gates of the various transistors as follows: Φ1 to the gate of transistor 25,/Φ1 to the gate of transistor 20, Φ2 to the gate of transistor 21, and /Φ2 to the gate of transistor 26.
Boosted clock signals are applied to the gates of the various transistors as follows: Φ1 to the gate of transistor 23, /Φ1 to the gate of transistor 18, Φ2 to the gate of transistor 17 and /Φ2 to the gate of transistor 24.
'654 patent, col. 4:11-19 (emphasis added). That excerpt, which describes Figure 3 of the Foss patents, illustrates that "clock sources," at least some of the time, may include "clock signals." Dr. Richard Foss, the first named inventor on the Foss patents, agrees with this position, having testified that there is no meaningful difference between a "clock source" applied to an inverter and its "clock signal" output. (See Foss 30(b)(6) Dep. at 125:15-19).

  Another problem with MOSAID's argument is that the patent disclaims the use of any "clock source," not just a "master clock source." Under MOSAID's definition of "clock source," there can be only one. However, that definition would exclude the embodiment depicted in Figure 1 and the "clock sources" used to charge boosting capacitors 9 and 11 because the Foss specifications clearly state that there are two different clock sources. See, e.g., '654 patent, 1:40-42 (referring to one clock source and then "another clock source"). Because MOSAID's proposed construction of "clock sources" does not comport with the patents themselves, it must be rejected.*fn12

  MOSAID tries to differentiate between the accused products and the prior art circuit shown in Figure 1 by arguing that the inverters shown in Figure 1 "represent the output stage of the oscillator clock source, and therefore the clock source output stage directly supplies charge to capacitors 9, 11,"*fn13 whereas the inverters in Infineon's products are not part of the actual "clock source," and therefore the "clock source" output is not directly supplied to the boosting capacitor. MOSAID's distinction, however, is unsupported and based solely on attorney argument. Contrary to MOSAID's argument that inverters 8 and 10 are part of the "clock source," the specification clearly states that the clock sources are connected through the inverters, i.e., the outputs of the clock sources are applied to the inverters, which in turn output the signals to the second terminal. See '654 patent 1:51-53 ("A clock source is connected through an inverter 8 and via capacitor 9 to node 4, and another clock source is connected through an inverter 10 through capacitor 11 to node 3.") and 6:30-32 ("[T]he prior art pump [Figure 1, which includes the inverters,] . . . is driven by an oscillator 40, which provides clock signals, e.g., Φ1, Φ2, /Φ1 and /Φ2.").

  This description of how the clock source is applied to the second terminal comports with an inventor's deposition testimony. Testifying as a 30(b)(6) witness, Dr. Foss stated in relevant part:
Q. And the output of the ring oscillator [, i.e., the clock source,] is the input to inverters eight and ten.
A. That is the presumption, yes.
* * *
Q. And the difference between phi 1 and phi 2 and input to inverters eight and ten is that it's the same as phi 1 and phi 2 but in undelayed and unamplified form, right?
A. Undelayed and unamplified form, yes.
(Foss 30(b)(6) Dep. at 125:7-19).

  In sum, the patentees used "clock signal" and "clock source" interchangeably. As a result, MOSAID's attempt to argue that the second terminal of the boosting capacitor in Infineon's accused products charge from a local "clock signal" rather than a "clock source" is inapt. There is no dispute that in the accused products, like the prior art, a "clock source" is supplied through an inverter to charge the second terminal of the boosting capacitor. Accordingly, the undisputed facts demonstrate that Hatteras and the other accused products use a "clock source" to charge the boosting capacitor, falling squarely within the clock source disclaimer. As a result, the accused products do not literally infringe claims 1-3, 5-9, 13-15, 17-21, and 24 of the '620 patent, claims 1, 10-11, and 20 of the '201 patent, and claims 1, 3-4 and 6 of the '654 patent.

  MOSAID argues in the alternative that even if the accused products do not meet this limitation literally, they meet it under the doctrine of equivalents. MOSAID, however, is wrong. Having disclaimed the use of clock sources to charge the boosting capacitor, MOSAID cannot use the doctrine of equivalents to recapture that which it specifically excluded from the claims. Festo Corp. v. Shoketsu Kinzoku Kogyo Kabushiki Co., 344 F.3d 1359, 1378 (Fed. Cir. 2003) ("The patentee cannot reach, through equivalency, that which was disclaimed in order to obtain the patent."); SciMed Life Sys., Inc. v. Advanced Cardiovascular Sys., Inc., 242 F.3d 1337, 1345 (Fed. Cir. 2001) ("Having specifically identified, criticized, and disclaimed the [accused structure], the patentee cannot now invoke the doctrine of equivalents to `embrace a structure that was specifically excluded from the claims.'") (quoting Dolly, Inc. v. Spalding & Evenflo Cos., 16 F.3d 394, 400 (Fed. Cir. 1994)). Consequently, the accused products do not infringe the asserted Foss claims, either literally or under the doctrine of equivalents.

  2. The "Second Switch" Limitation

  MOSAID moves for summary judgment that Hatteras contains a circuit that satisfies the "second switch" limitation of the '654 patent — "a second switch between the first terminal of the boosting capacitor and a capacitive load."*fn14 The parties designate the circuit in question as "S2." Infineon argues that Hatteras does not infringe the ...


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